Linear and two-dimensional detector arrays have been based hitherto on the read-out of an array of pyroelectric elements by a charge-coupled device (CCD). These CCD-hybrid detectors are discussed in a recent article by R Watton et al entitled "Performance and Technologies for Linear and Two-Dimensional Pyroelectric Arrays", IEE Conference Publications No. 228, 2nd International Conference on Advanced Infrared Detectors and Systems, pp 49-53 (1983). However in this CCD-hybrid arrangement, both the signal and noise on each element are sampled and held at the pixel by the use of the CCD input well. This results in aliasing of the noise at the pixel. In particular the thermal noise in the CCD gate, when aliased, gives rise to a noise of (4/3 kT.alpha./C).sup.1/2 volts R.M.S, where C is the detector capacitance and .alpha. the injection efficiency. Since the pyroelectric voltage signal developed is independent of the element area, A, the signal to noise ratio for this dominant noise source is proportional to A.sup.1/2, ie it is proportional to the element pitch.
The current trend, in the development of large arrays, is to reduce element pitch but, from the above result, this occurs in the CCD design at the expense of performance. CCD readout is effectively limited to an inter-element pitch of 100 .mu.m or greater to achieve an acceptable signal to noise ratio with conventional technology.
Other useful contemporary references relating to CCD-pyroelectric hybrids are given as follows:
R. Watton, et al, Infrad Physics 22 pp 259-275 (1982); PA0 R. Watton, et al; SPIE Proceedings Vol 395 (1983); and, PA0 D. Buss, et al, IEEE Trans EL Devices, Vol ED-27, 998-1000 (1980). PA0 (1) a row of thermal detector elements disposed to receive radiation from a scene, PA0 (2) a row output line arranged to relay detector element signals to a common row output, PA0 (3) a respective power amplifier associated with each detector element, each power amplifier being arranged to amplify detector element signals for output to the row output line and to decouple detector element capacitance from that of the row output line, PA0 (4) modulating means arranged to modulate radiation from the scene such that each detector element experiences alternate light and dark time intervals and becomes illuminated in sequence along the row, PA0 (5) addressing means synchronised with the modulating means and arranged to address the power amplifiers sequentially and sample their signals to the common row output to provide alternate light and dark sets of signals, and PA0 (6) a band pass filter arranged to receive light and dark sets of signals from the common row output, the filter having transmission characteristics to pass detector element output signals and including both an anti-aliasing low pass filter and a high pass filter arranged to extract respective difference signals from each detector element's light and dark output signals.
As an alternative to the CCD approach, detector elements have been read-out by means of multiplexed matrix switches and bus lines. Examples of this alternative approach are described by G S Hopper, U.S. Pat. No. 4,162,402. As described there, a row of ferro-electric detector elements is coupled to a bus line via a row of a like number of metal-oxide semiconductor field-effect transistor (MOSFET) switches. The bus line signal is relayed to a video processor via a common amplifier.
A detector similar to that considered here is described by A. Carlson et al in an article entitled "Solid-state pyroelectric imaging system", SPIE vol 267 Staring Infrared Focal Plane Technology pp 86-98 (1981). It includes a row of pyroelectric thermal detector elements, a semiconductor support layer, a respective high impedance input preamplifier with associated switch embodied in the layer and provided for each element, together with a common bus line. The row of pyroelectric elements is coupled to a bus line via the switchable preamplifiers, each of which comprises a double-gate junction field-effect transistor (JFET). Each detector element is connected to one gate of its corresponding JFET and the signal voltage on this gate controls the flow of current through the transistor channel. This preamplifier is switched by means of a voltage address applied to its other gate. A problem, associated with this choice of preamplifier, is the relatively significant magnitude of gate leakage current. This places a severe restriction on the transistor construction and operation. The silicon array of JFET's must be produced using special processing techniques in order to keep the leakage current below about 10.sup. -13 A. The bus line is followed by an impedance converter and an analog shift register.